1. Field of the Invention
The present invention relates to a data acceleration device and a data transmission apparatus using the same; and, more particularly, to a data acceleration device and a data transmission apparatus using the same, which is capable of decreasing an entire signal delay in a data transmission line of a semiconductor device with a longer transmission distance and a larger load.
2. Description of Related Art
Currently, a semiconductor chip size becomes larger as a semiconductor device (particularly, DRAM) becomes more integrated. This large chip size causes an increase in the distance and a load of a signal transmission line within the DRAM. As such, as the distance and load of signal transmission line increases, a delay of data transmitted over the signal transmission line tends to degrade more and more.
To decrease this transmission delay phenomenon of the data, in general, a repeater is utilized where FIG. 1 shows a circuit diagram illustrating composition of a conventional data transmission apparatus using such a repeater.
As shown in FIG. 1, the conventional data transmission apparatus is comprised of a repeater 10 having a simple inverter chain wherein the repeater 10 functions to amplify a signal level of the data from an input port at a prescribed level and then sent it to an output port, without attenuation.
Herein, in case that an input signal is transited from low level to high level, or from a high to a low level conversely, in order to have the same delay maintained, it is designed so that the logic threshold level of each inverter constituting the repeater 10 is set to a value of (high level−low level)/2. The logic threshold level is defined as a reference signal level for each inverter to decide whether the input signal level is high or low. Thus, the repeater 10 formed by the chain of inverters as mentioned above initiates to operate when, if the input signal is transited from a low level to a high level, the signal level rises up to (high level−low level)/2. Likewise, the repeater 10 starts to operate when the input signal level comes down up to (high level−low level)/2 if the input signal is transited from high to low level.
In the prior art data transmission apparatus, accordingly, there exists any operation delay since the repeater 10 operates when the input signal rises or falls to the logic threshold level from a low or high level. Moreover, this operation delay generally results in a delay in the data transmission.